High-speed data communication, such as exemplified in local area networks, must be synchronized as between the data transmitter and receiver, at least for the length of the minimum data group or packet sent, in order to be effective. Conventional asynchronous communications systems permit participating data transmitters and receivers to initiate and recognize the beginning of each data packet. They are thus capable of dealing variable time between transmission periods between data packets yet equally capable of becoming mutually synchronous relative to the currently transmitted data packet. Indeed, both conventional asynchronous and synchronous communication systems must be synchronous with respect to the transmission and reception of data within the data packet. That is, there must be a mutual, synchronous data transfer rate for the entire length of the transfer. Failure to maintain synchronism inevitably results in the miscommunication and, therefore, effective loss of the data.
A difference in data transmitter and data receiver transfer rates may arise due to a variety of reasons. Thermal drift in a base frequency oscillator circuit of either the transmitter or receiver as well as a simple misadjustment of one base frequency with respect to the other are but two common sources of a frequency difference.
A conventional elastic buffer is commonly used to adjust the data rate of a data stream so as to synchronize it with another desired data rate. An elastic buffer is a variant of the conventional first-in-first-out (FIFO) buffer. Elastic buffers significantly differ in that they allow for the reading and writing of data at different, relatively independent rates. Management of data within the elastic buffer is typically performed by maintaining address pointers that generally point to the memory locations within the buffer that contain the currently oldest written, but not yet read, and the currently oldest read, but not yet written, data in the buffer. These pointers progressively establish the memory locations within the buffer that are to be next read and written, respectively, as the data stream passes through. Since the current read and write memory locations are not fixed relative to one another, the buffer can elastically compensate for any difference in the transmitter rate that data is written to and the receiver rate that data is read from the buffer. Consequently, an elastic buffer can dynamically adjust the transfer rate of a data stream so as to effectively synchronize a data transmitter with a data receiver.
There are, however, a number of problems associated with the use of elastic buffers. One problem pertains to the need to ensure that data is read from the buffer in the same order that it was written to the buffer. Reading data that has not been written or writing data over data that has not yet been read destroys the integrity of at least the data packet being transferred. This is commonly known as a data overflow/underflow fault condition and is naturally to be avoided.
A closely related problem involves the occurrence of metastable logic states. Metastable states typically arise as data is written to and read from a memory location before the voltage potential representing the data written has properly propagated and settled. The voltage potential effectively read may not properly represent the data written and, by changing during the read operation, may propagate metastable logic states through the associated read circuitry. As the memory location has not been read before it was written, there is properly no indication of an overflow/underflow or other fault condition. Thus, the integrity of the data being transferred can be destroyed without notice, at least unless some other system of checking data integrity is provided.
A further difficulty involves the proper control of the elastic buffer. As there is no necessary phase relationship between the transmitter and receiver clock signals, they may be up to 180 degrees out of phase relative to one another. Consequently, events that are significant to the operation of the elastic buffer, such as initializing on the detection of the beginning of a data transfer, must be coordinated with respect to both the transmitter and receiver data rates and any current phase difference between them. The occurrence and propagation of metastable logic states throughout the control circuitry of conventional elastic buffers is, consequently, a commonly recognized problem.